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INTEGRATED CIRCUITS
DATA SHEET
SAA7706H Car radio Digital Signal Processor (DSP)
Product specification File under Integrated Circuits, IC01 2001 Mar 05
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
CONTENTS 1 1.1 1.2 2 3 4 5 6 7 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.5 8.6 8.6.1 8.7 8.7.1 8.7.2 8.7.3 8.7.4 8.7.5 8.7.6 8.8 8.8.1 8.9 8.10 8.11 8.12 8.12.1 8.12.2 FEATURES Hardware Software APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Analog front-end The realization of common mode input with AIC Realization of the auxiliary input with volume control Realization of the FM input control Pins VDACN1, VDACN2 and VDACP Pin VREFAD Supply of the analog inputs The signal audio path for input signals CD, TAPE, AUX, PHONE, NAV and AM Signal path for level information Signal path from FM_MPX input to IAC and stereo decoder Noise level Mono or stereo switching The automatic lock system DCS clock The Interference Absorption Circuit (IAC) General description The Filter Stream DAC (FSDAC) Interpolation filter Noise shaper Function of pin POM Power-off plop suppression Pin VREFDA for internal reference Supply of the filter stream DAC Clock circuit and oscillator Supply of the crystal oscillator The phase-locked loop circuit to generate the DSPs and other clocks Supply of the digital part (VDDD3V1 to VDDD3V4) CL_GEN, audio clock recovery block External control pins DSP1 DSP2 8.15.1 8.15.2 8.15.3 8.15.4 8.16 8.17 9 9.1 9.2 9.3 9.4 9.5 9.5.1 9.6 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 8.13 8.14 8.14.1 8.14.2 8.14.3 8.15
SAA7706H
I2C-bus control (pins SCL and SDA) Digital serial inputs/outputs and SPDIF inputs General description digital serial audio inputs/outputs General description SPDIF inputs (SPDIF1 and SPDIF2) Digital data stream formats RDS demodulator (pins RDS_CLOCK and RDS_DATA) Clock and data recovery Timing of clock and data signals Buffering of RDS data Buffer interface DSP reset Test mode connections (pins TSCAN, RTCB and SHTCB) I2C-BUS FORMAT Addressing Slave address (pin A0) Write cycles Read cycles SAA7706H hardware registers SAA7706H DSPs registers I2C-bus memory map specification LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS RDS AND I2S-BUS TIMING I2C-BUS TIMING SOFTWARE DESCRIPTION APPLICATION DIAGRAM PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2001 Mar 05
2
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
1 1.1 FEATURES Hardware
SAA7706H
* 5-bitstream 3rd-order sigma-delta Analog-to-Digital Converters (ADCs) with anti-aliasing broadband input filter * 1-bitstream 1st-order sigma-delta ADC with anti-aliasing broadband input filter * 4-bitstream Digital-to-Analog Converters (DACs) with 128-fold oversampling and noise shaping * Integrated semi-digital filter; no external post filter required for DAC * Dual media support: allowing separate front-seat and rear-seat signal sources and separate control * Simultaneous radio and audio processing * Digital FM stereo decoder * Digital FM interference suppression * RDS demodulation via separate ADC; with buffered output option * Two mono Common-Mode Rejection Ratio (CMRR) input stages for voice signals from phone and navigation inputs * Phone and navigation mixing at DAC front outputs * Two stereo CMRR input stages (CD-walkman and CD-changer etc.) * Analog single-ended TAPE and AUX input * Separate AM-left and AM-right inputs in the event of use of external AM stereo decoder * One digital input: I2S-bus or LSB-justified format * Two digital inputs: SPDIF format * Co-DSP support via I2S-bus or LSB-justified format * Audio output short-circuit protected * I2C-bus controlled (including fast mode) * MOST bus interfacing (details in separate manual) * Phase-locked loop derives the internal clocks from one common fundamental crystal oscillator * Combined AM/FM level input * Pin compatible with SAA7705 and SAA7708 * All digital inputs are tolerant of 5 V input levels * All analog inputs have high GSM immunity * Low number of external components required * -40 to +85 C operating temperature range * Easy applicable. 1.2 Software
* Improved FM weak signal processing * Integrated 19 kHz MPX filter; de-emphasis and stereo detection * Electronic adjustments: FM or AM level, FM channel separation, Dolby(R)(1) level * Baseband audio processing (treble, bass, balance, fader and volume) * Four channel 5-band parametric equalizer * 9-bands mono audio spectrum analyzer * Extended beep functions with tone sequencer for phone rings * Large volume jumps e-power interpolated to prevent zipper noise * Dual media support; allowing separate front-seat and rear-seat signal sources and separate control * Dynamic loudness or bass boost * Audio level monitor * Tape equalization and Music Search System (MSS) detection for tape * Dolby-B tape noise reduction (at 44.1 kHz only) * Dynamics compression available in all modes * CD de-emphasis processing * Voice-over possibility for phone and navigation signals * Improved AM signal processing * Digital AM CQUAM stereo decoder (not in all rom_codes available) * Digital AM interference suppression * Soft audio mute * RDS update processing: pause detection, mute and signal-quality sensor-freeze * General purpose tone generator
(1) Dolby -- Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111, USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby Laboratories Licensing Corporation.
2001 Mar 05
3
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
* Noise generator allows for frequency response measurements * Boot-up ROM for fast start-up * Signal level, noise and multipath detection for AM or FM signal quality information * AM co-channel and adjacent channel detection (not in all rom_codes available). 2 APPLICATIONS * RDS-demodulation
SAA7706H
* FM and AM weak signal processing (soft mute, sliding stereo and high cut) * Dolby-B tape noise reduction * CD de-emphasis function * Audio controls for volume, balance, fader, tone and dynamics compression. Some functions have been implemented in hardware (FM stereo decoder, RDS-demodulator and FM Interference Absorption Circuit (IAC) and are not freely programmable. Digital audio signals from external sources with the Philips I2S-bus and the LSB-justified 16, 18, 20 and 24 bits format or SPDIF format are accepted. The big advantage of this SAA7706H device is the `dual media support'; this enables independent front seat and rear seat audio sources and control.
* High-end car radio systems. 3 GENERAL DESCRIPTION
The SAA7706H performs all the signal functions in front of the power amplifiers and behind the car radio tuner AM and FM outputs and the CD, tape and phone inputs. These functions are: * Interference absorption * Stereo decoding for FM and AM (stereo) 4 QUICK REFERENCE DATA SYMBOL Supplies VDD IDDD IDDA Ptot FM_MPX input Vi(con)(max)(rms) THD maximum conversion input level (RMS value) total harmonic distortion operating supply voltage supply current of the digital part supply current of the analog part total power dissipation PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
all VDD pins with respect to VSS DSP1 at 50 MHz; DSP2 at 62.9 MHz zero input and output signal DSP1 at 50 MHz; DSP2 at 62.9 MHz
3 - - -
3.3 110 40 540
3.6 150 60 750
V mA mA mW
THD < 1%; VOLFM = 00H input signal 0.368 V (RMS) at 1 kHz; bandwidth = 19 kHz; VOLFM = 00H
0.33 - -
0.368 -70 0.03
- -65 0.056
V dB %
S/N
signal-to-noise ratio input stereo
input signal at 1 kHz; 75 bandwidth = 40 kHz; 0 dB reference = 0.368 V (RMS); VOLFM = 00H
81
-
dB
CD, TAPE, AUX and AM inputs Vi(con)(max)(rms) maximum conversion input level (RMS value) THD < 1% 0.6 0.66 - V
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
SYMBOL THD
PARAMETER total harmonic distortion
CONDITIONS input signal 0.55 V (RMS) at 1 kHz; bandwidth = 20 kHz input signal at 1 kHz; bandwidth = 20 kHz; 0 dB reference = 0.55 V (RMS)
MIN. -
TYP. -85
MAX. -75
UNIT dB
S/N
signal-to-noise ratio
85
90
-
dB
FSDAC (THD + N)/S total harmonic distortion-plus-noise to at 0 dB signal ratio (measured with system at -60 dB; A-weighted one) signal-to-noise ratio (measured with system one) code = 0; A-weighted - - - -90 -37 105 -85 - - dB dB dB
S/N
Crystal oscillator fxtal 5 crystal frequency ORDERING INFORMATION TYPE NUMBER SAA7706H PACKAGE NAME QFP80 DESCRIPTION plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT318-2 - 11.2896 - MHz
2001 Mar 05
5
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DSP2_INOUT4
DSP2_INOUT3
DSP2_INOUT2
VDACP VDACN1 PHONE PHONE_GND
1 2 71 73
74
76 75
46 36 22
49 50 53 54 47 37 23
48 51 52 55
41 40 39 38 19 18 15 17 11 10 VDDA2 VSSA2 POM
DSP2_INOUT1
DSP1_OUT2
DSP1_OUT1
DSP1_IN2
DSP1_IN1
VDDD3V5
VDDD3V6
VDDD3V7
VDDD3V1
VDDD3V2
VDDD3V3
VDDD3V4
VSSD3V1
VSSD3V2
VSSD3V3
VSSD3V4
VSSD3V5
VSSD3V6
VSSD3V7
VDACN2
VDDA1
VSSA1
RDS_CLOCK
DSP_RESET
SHTCB
TSCAN
SYSFS
RTCB
CD_CLK
SPDIF2
RDS_DATA
VSS(OSC)
OSC_OUT
CD_WS
VDD(OSC)
CD_DATA
OSC_IN
SPDIF1
SCL
TP1
SDA
A0
2001 Mar 05
NAV_GND LEVEL CD_L CD_R CD_(L)_GND CD_R_GND VREFAD 4 3 72 70 77 14 78
6
Philips Semiconductors
Car radio Digital Signal Processor (DSP)
BLOCK DIAGRAM
MONO CMRR INPUTS LEVELADC
5 PHONE VOLUME SIGNAL LEVEL
+
DSP1 QUAD FSDAC
16
FLV
STEREO CMRR INPUTS
SAA7706H
SIGNAL QUALITY
+
13 9
FRV RLV RRV VREFDA IIS_OUT1 IIS_OUT2 IIS_CLK IIS_WS IIS_IN1 IIS_IN2
IAC STEREO ADC1 67 66 7 8 69 68 80 79 61 RDS DEMODULATOR XTAL OSCILLATOR I2S-BUS ANALOG SOURCE SELECTOR STEREO ADC2
STEREO DECODER
6 DIGITAL SOURCE SELECTOR 12 34 A DIGITAL SOURCE SELECTORS DSP2 B DIGITAL I/O 35 30 33 31 32
6
AM_L/NAV AM_R/AM AUX_L AUX_R TAPE_L TAPE_R FM_MPX FM_RDS SEL_FR
MONO ADC3
SPDIF
I2C-BUS 20 LOOPO
43 44 45
21
60
59 62 65 63
64 26 29 27 28
24 25
57 58 56
42
MGT457
Product specification
SAA7706H
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
7 PINNING SYMBOL VDACP VDACN1 LEVEL PIN 1 2 3 PIN TYPE apio apio apio gsmcap DESCRIPTION
SAA7706H
positive reference voltage ADC1, ADC2, ADC3 and level-ADC ground reference voltage ADC1 LEVEL input pin; via this pin the level of the FM signal or level of the AM signal is fed to the DSP1; the level information is used in the DSP1 for dynamic signal processing common mode reference input pin of the navigation signal (pin AM_L/NAV) power-on mute of the QFSDAC; timing is determined by an external capacitor rear; right audio output of the QFSDAC left channel of analog AUX input right channel of analog AUX input rear; left audio output of the QFSDAC ground supply analog part of the QFSDAC and SPDIF bitslicer positive supply analog part of the QFSDAC and SPDIF bitslicer voltage reference of the analog part of QFSDAC front; right audio output of the QFSDAC common-mode reference input pin for analog CD_R or TAPE_R in the event of separated ground reference pins for left and right are used flag input/output 2 of the DSP2-core (DSP2-flag) I2C-bus configurable front; left audio voltage output of the QFSDAC flag input/output 1 of the DSP2-core (DSP2-flag) I2C-bus configurable flag input/output 3 of the DSP2-core (DSP2-flag) I2C-bus configurable flag input/output 4 of the DSP2-core (DSP2-flag) I2C-bus configurable SYSCLK output (256fs) for test purpose only; this pin may be left open or connected to ground positive supply (peripheral cells only) ground supply (peripheral cells only) SPDIF input 2; can be selected instead of SPDIF1 via I2C-bus bit SPDIF input 1; can be selected instead of SPDIF2 via I2C-bus bit system fs clock input digital CD-source word select input; I2S-bus or LSB-justified format digital CD-source left-right data input; I2S-bus or LSB-justified format digital CD-source clock input I2S-bus or LSB-justified format clock output for external I2S-bus receiver; for example headphone or subwoofer data 1 input for external I2S-bus transmitter; e.g. audio co-processor data 2 input for external I2S-bus transmitter; e.g. audio co-processor word select output for external I2S-bus receiver; for example headphone or subwoofer data 1 output for external I2S-bus receiver or co-processor data 2 output for external I2S-bus receiver or co-processor 7
NAV_GND POM RRV AUX_L AUX_R RLV VSSA2 VDDA2 VREFDA FRV CD_R_GND DSP2_INOUT2 FLV DSP2_INOUT1 DSP2_INOUT3 DSP2_INOUT4 LOOPO TP1 VDDD3V7 VSSD3V7 SPDIF2 SPDIF1 SYSFS CD_WS CD_DATA CD_CLK IIS_CLK IIS_IN1 IIS_IN2 IIS_WS IIS_OUT1 IIS_OUT2 2001 Mar 05
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
apio gsmcap apio apio apio apio apio vssco vddco apio apio apio bpts5thdt5v apio bpts5thdt5v bpts5thdt5v bpts5thdt5v bpts5tht5v ipthdt5v vdde vsse apio apio ipthdt5v ipthdt5v bpts10thdt5v ipthdt5v ots10ct5v ipthdt5v ipthdt5v ots10ct5v ots10ct5v ots10ct5v
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
SYMBOL VDDD3V6 VSSD3V6 DSP1_IN1 DSP1_IN2 DSP1_OUT1 DSP1_OUT2 DSP_RESET RTCB SHTCB TSCAN VDDD3V5 VSSD3V5 VDDD3V1 VSSD3V1 VSSD3V2 VDDD3V2 VDDD3V3 VSSD3V3 VSSD3V4 VDDD3V4 A0 SCL SDA RDS_CLOCK RDS_DATA SEL_FR VSS(OSC) OSC_IN OSC_OUT VDD(OSC) AM_R/AM AM_L/NAV TAPE_R TAPE_L CD_R PHONE CD_L 2001 Mar 05
PIN 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN TYPE vdde vsse bpts10thdt5v bpts10thdt5v op4mc op4mc iptut5v ipthdt5v ipthdt5v ipthdt5v vdde vsse vddi vssis vssco vddco vddco vssco vssis vddi ipthdt5v iptht5v iic400kt5v bpts10tht5v ops10c iptht5v vssco apio apio vddco apio gsmcap apio gsmcap apio gsmcap apio gsmcap apio gsmcap apio gsmcap apio gsmcap
DESCRIPTION positive supply (peripheral cells only) ground supply (peripheral cells only) flag input 1 of the DSP1-core flag input 2 of the DSP1-core flag output 1 of the DSP1-core flag output 2 of the DSP1-core general reset of chip (active LOW) asynchronous reset test control block; connect to ground (internal pull-down) shift clock test control block (internal pull-down) scan control active high (internal pull-down) positive supply (peripheral cells only) ground supply (peripheral cells only) positive supply (core only) ground supply (core only) ground supply (core only) positive supply (core only) positive supply (core only) ground supply (core only) ground supply (core only) positive supply (core only) slave sub-address I2C-bus selection or serial data input test control block serial clock input I2C-bus serial data input/output I2C-bus radio data system bit clock output or RDS external clock input I2C-bus bit controlled radio data system data output AD input selection switch to enable high ohmic FM_MPX input at fast tuner search on FM_RDS input ground supply (crystal oscillator only) crystal oscillator input crystal oscillator output positive supply (crystal oscillator only) right channel AM audio frequency or AM input in the event of mono; analog input pin left channel AM audio frequency or input of common mode navigation signal; analog input pin right channel of analog TAPE input left channel of analog TAPE input right channel of analog CD input common mode PHONE signal, analog input pin left channel of analog CD input 8
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
SYMBOL PHONE_GND VDDA1 VSSA1 VDACN2 CD_(L)_GND VREFAD FM_RDS FM_MPX Table 1
PIN 73 74 75 76 77 78 79 80
PIN TYPE apio gsmcap vddco vssco apio apio gsmcap apio apio gsmcap apio gsmcap
DESCRIPTION common mode reference input pin of the PHONE signal positive supply analog (ADC1, ADC2, ADC3 and level-ADC only) ground supply analog (ADC3 and level-ADC only) ground reference voltage (ADC2) common mode reference input pin for analog CD or TAPE or in the event of separated ground reference pins used for CD_L or TAPE_L common mode reference voltage ADC1, ADC2, ADC3 and level-ADC FM RDS signal; analog input pin FM multiplex signal; analog input pin
Brief explanation of used pin types EXPLANATION 3-state I/O analog; I/O pad cell; actually pin type vddco 3-state I/O analog; I/O pad cell; actually pin type vddco with high GSM immunity 43 MHz bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; TTL; hysteresis; pull-down; 5 V tolerant 21 MHz bidirectional pad; push-pull input; 3-state output; 10 ns slew rate control; TTL; hysteresis; 5 V tolerant 21 MHz bidirectional pad; push-pull input; 3-state output; 10 ns slew rate control; TTL; hysteresis; pull-down; 5 V tolerant I2C-bus pad; 400 kHz I2C-bus specification; TTL; 5 V tolerant input pad buffer; TTL; hysteresis; 5 V tolerant input pad buffer; TTL; hysteresis; pull-down; 5 V tolerant input pad buffer; TTL; pull-up; 5 V tolerant output pad buffer; 4 mA output drive; CMOS; slew rate control; 50 MHz output pad buffer; 3-state, 10 ns slew rate control; CMOS; 5 V tolerant output pad buffer; 4 mA output drive; CMOS; slew rate control; 21 MHz VDD supply peripheral only VSS supply peripheral only VDD supply to core only VSS supply to core only (vssco does not connect the substrate) VDD supply to core and peripheral VSS supply to core and peripheral; with substrate connection
PIN TYPE apio apio gsmcap bpts5thdt5v bpts10tht5v bpts10thdt5v iic400kt5v iptht5v ipthdt5v iptut5v op4mc ots10ct5v ops10c vdde vsse vddco vssco vddi vssis
2001 Mar 05
9
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
77 CD_(L)_GND
handbook, full pagewidth
73 PHONE_GND
67 AM_L/NAV
VDACP VDACN1 LEVEL
65 VDD(OSC) 64 OSC_OUT 63 OSC_IN 62 VSS(OSC) 61 SEL_FR 60 RDS_DATA 59 RDS_CLOCK 58 SDA 57 SCL 56 A0 55 VDDD3V4 54 VSSD3V4 53 VSSD3V3 52 VDDD3V3 51 VDDD3V2 50 VSSD3V2 49 VSSD3V1 48 VDDD3V1 47 VSSD3V5 46 VDDD3V5 45 TSCAN 44 SHTCB 43 RTCB 42 DSP_RESET 41 DSP1_OUT2 DSP1_OUT1 40
1 2 3
NAV_GND 4 POM RRV AUX_L AUX_R RLV 5 6 7 8 9
VSSA2 10 VDDA2 11 VREFDA 12
SAA7706H
FRV 13 CD_R_GND 14 DSP2_INOUT2 15 FLV 16 DSP2_INOUT1 17 DSP2_INOUT3 18 DSP2_INOUT4 19 LOOPO 20 TP1 21 VDDD3V7 22 VSSD3V7 23 SPDIF2 24 SPDIF1 25 SYSFS 26 CD_WS 27 CD_DATA 28 CD_CLK 29 IIS_CLK 30 IIS_IN1 31 IIS_IN2 32 IIS_WS 33 IIS_OUT1 34 IIS_OUT2 35 VDDD3V6 36 VSSD3V6 37 DSP1_IN1 38 DSP1_IN2 39
66 AM_R/AM
80 FM_MPX
79 FM_RDS
76 VDACN2
78 VREFAD
68 TAPE_R
69 TAPE_L
74 VDDA1
75 VSSA1
71 PHONE
70 CD_R
72 CD_L
MGT458
Fig.2 Pinning diagram.
2001 Mar 05
10
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
8 8.1 FUNCTIONAL DESCRIPTION Analog front-end
SAA7706H
The analog front-end consists of two identical sigma-delta stereo ADCs (ADC1 and ADC2) with several input control blocks for handling common mode signals and acting as input selector. A mono version (ADC3) is added for handling RDS signals. Also a first-order sigma-delta ADC for tuner level information is incorporated. The switches S1 and S2 select (see Fig.3) between the FM_MPX/FM_RDS and the CD, TAPE, AUX, AM, PHONE and NAV connection to ADC1 and ADC2. The inputs CD, TAPE, AUX, AM, PHONE and NAV can be selected with the audio input controls (AIC1/2). The ground reference (G0 and G1) can be selected to be able to handle common mode signals for CD or TAPE. The ground reference G0 is connected to an external pin and G1 is internally referenced (see Fig.4).
The PHONE and NAV inputs have their own CMRR input stage and can be redirected to ADC1/2 via the Audio Input Control (AIC). For pin compatibility with SAA7704, SAA7705 and SAA7708 the AM is combined with the NAV input. It is also possible to directly mix PHONE or NAV (controlled with MIXC) with the front FSDAC channels after volume control. The FM inputs (FM_MPX/FM_RDS) can be selected with external pin SEL_FR. The FM and RDS input sensitivity can be adjusted with VOLFM and VOLRDS via I2C-bus.
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
CLKLEVEL LEVELO
LEVEL
3 VOLRDS(5:0) S3 1 0 MUX VOLFM(5:0) 0 1 MUX
LEVEL-ADC
CLKADC2 MONO (RDS) ADC3 RDS
SEL_FR FM_RDS FM_MPX CD_L TAPE_L
61 79 80 72 69 GNDC1
ADF3
AUX_L
7 0 1 MUX 70 68 66 8 77 78 14
x00 AIC1(2:0) GNDRC1 x01 x10 MUX 011 1 111 0 MUX
S1 0 1 MUX 0 1 MUX STEREO ADC1 LEFT1 ADF1_a RIGHT1
CD_R TAPE_R AM_R/AM AUX_R CD_(L)_GND VREFAD CD_R_GND
x00 x01 x10 MUX 011 111
0 1 MUX
CLKADC2 fmhsnr_adc1 charge_pump
GNDC2 0 1 MUX
x00 AIC2(2:0) GNDRC2 x01 x10 MUX 1 011 0 111 MUX
S2 0 1 MUX 0 1 MUX STEREO ADC2 LEFT2 ADF1_b RIGHT2
MIDREF
x00 x01 x10 MUX 011 111 MIXC
0 1 MUX
CLKADC2 fmhsnr_adc2 VOLMIX(5:2) MIX
PHONE PHONE_GND AM_L/NAV NAV_GND
71 73 67 4
CMRR
1 0 MUX VOLMIX(4:0)
CMRR
located in FIRDAC
MGT459
Fig.3 Analog front-end switch diagram.
2001 Mar 05
12
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
8.1.1 THE REALIZATION OF COMMON MODE INPUT WITH AIC
SAA7706H
A high common mode rejection ratio can be created by the use of the ground return pin. Pin CD_(L)_GND can be used in the case that the left and right channel have one ground return line. CD_(L)_GND and CD_R_GND can be used for separated left and right ground return lines. The ground return lines can be connected via the switch GNDC1/2 and GNDRC1/2 (see Fig.4) to the plus input of the second operational amplifier in the signal path. The signal of which a high common mode rejection ratio is required has a signal and a common signal as input. The common signal is connected to the CD_(L)_GND and/or CD_R_GND input. The actual input can be selected with audio input control AIC1/2(1:0).
In Fig.4 the CD input is selected. In this situation both signal lines going to S1/2 in front of the ADC will contain the common mode signal. The ADC itself will suppress this common mode signal with a high rejection ratio. The inputs CD_L and CD_R in this example are connected via an external resistor tap of 82 k and 100 k to be able to handle larger input signals. The 100 k resistors are needed to provide a DC biasing of the operational amplifiers OA1 and OA2. The 1 M resistor provides DC biasing of OA3 and OA4. If no external resistor tap is needed the resistors of 100 k and 1 M still have to provide DC biasing. Only the 82 k resistor can be removed. The impedance level in combination with parasitic capacitance at input CD_L or CD_R determines for a great deal the achievable common rejection ratio.
handbook, full pagewidth
10 k 82 k LEFT CD_L 72 00 01 10 MUX 11 G1 GROUND LEFT CD_(L)_GND 1 M VREFAD 78 77 G0
10 k to MUX S1/2 10 k
OA1
OA3 AIC1/2(1:0)
100 k
from CD-player analog
GNDC1/2 GNDRC1/2 MIDREF
1 M CD_R_GND GROUND RIGHT 100 k 82 k RIGHT CD_R 70 00 01 10 MUX 11 10 k 10 k to MUX S1/2 10 k OA2 OA4
MGT460
14
off-chip
on-chip
Fig.4 Example of the use of common mode analog input in combination with input resistor tap.
2001 Mar 05
13
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
0 dB (full-scale) 660 mV (RMS) Audio GAIN ADC AUDIO DIGITAL FILTER 5 dB GAIN DSP2
STEREO DECODER 3 dB GAIN
DSP1
-2 dB (full-scale)
MGT461
Fig.5 Audio gain through ADC and digital filter path to DSP.
8.1.2
REALIZATION OF THE AUXILIARY INPUT WITH VOLUME
CONTROL
8.1.3
REALIZATION OF THE FM INPUT CONTROL
A differential input with volume control for mixing to the front left or front right of both DAC outputs is provided. The inputs consist of a PHONE and NAV input. Both are accompanied with their ground return lines. After selection of PHONE or NAV the volume can be changed from about +18 to -22.5 dB in 27 steps and mute (MIX output). This signal can be added to the left and/or right front DAC channels. The output signals of both input circuits can also be switched to ADC1 and/or ADC2, depending on the settings of audio input control 1 (AIC1) and audio input control 2 (AIC2), without volume control (see Fig.3).
The gain of the circuit has a maximum of 2.26 (7.08 dB). This results in an input level of 368 mV for full-scale, which means 0 dB (full-scale) at the DSP1 input via the stereo decoder (see Fig.6). The gain can be reduced in steps of 1.5 dB. When the gain is set to -3.4 dB the input level becomes 1229 mV for full-scale. This setting accounts for the 200 mV (RMS) input sensitivity at 22.5 kHz sweep and a saturation of the input at 138 kHz sweep. RDS update: for RDS update the fast access pin SEL_FR must be made HIGH. In that case the FM_RDS signal also goes through the path that was set for FM_MPX. In this situation the signal must be obtained via the FM_RDS input and a noise sample can be retrieved. The input FM_MPX gets high-ohmic. Charging of the coupling capacitor connected to pin FM_MPX is no longer possible.
handbook, full pagewidth
831 mV (RMS) FM GAIN ADC AUDIO DIGITAL FILTER 5 dB GAIN DSP2
0 dB (full-scale)
STEREO DECODER 3 dB GAIN
DSP1
MGT462
Fig.6 FM gain path through stereo decoder to DSP1.
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
8.1.4 PINS VDACN1, VDACN2 AND VDACP 8.1.6
SAA7706H
SUPPLY OF THE ANALOG INPUTS
These pins are used as negative and positive reference for the ADC1, 2, 3 and the level-ADC. They have to be directly connected to the VSSA1 and filtered VDDA1 for optimal performance (see Figs 25 and 26). 8.1.5 PIN VREFAD
The analog input circuit has separate power supply connections to allow maximum filtering. These pins are VSSA1 for the analog ground and VDDA1 for the analog power supply. 8.2 The signal audio path for input signals CD, TAPE, AUX, PHONE, NAV and AM
Via this pin the midref voltage of the ADCs is filtered. This midref voltage is used as half supply voltage reference of the ADCs. External capacitors (connected to VSSA1) prevent crosstalk between switch cap DACs of the ADCs and buffers and improves the power supply rejection ratio of all components. This pin is also used in the application as reference for the inputs TAPE and CD (see Fig.4). The voltage on pin VREFAD is determent by the voltage on pins VDACP and VDACN1 or VDACN2 and is found as: V VDACP - V VDACN1,2 V VREFAD = --------------------------------------------------2
The left and right channels are converted and down-sampled by the ADF1_a, ADF1_b. This data stream is converted into a serial format and fed to the DSP1 and DSP2 source selectors. In Figs 7 and 8 the overall and detailed frequency response curves of the analog-to-digital audio decimation path based on a 44.1 kHz sample frequency are shown.
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0
MGT463
(dB) -50
-100
-150
-200
-250
0
100
200
300
400
f (kHz)
500
Fig.7
Overall frequency response curve analog-to-digital audio path decimation based on a 44.1 kHz sample frequency.
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
20
MGT464
(dB) 0 -20 -40 -60 -80 -100 -120 -140
0
10
20
30
40
f (kHz)
50
Fig.8
Detailed frequency response curve analog-to-digital audio path decimation based on a 44.1 kHz sample frequency.
2001 Mar 05
16
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
8.3 Signal path for level information
SAA7706H
For FM weak signal processing, for AM and FM purposes (absolute level and multipath) a level input is implemented (pin LEVEL). In the event of radio reception the clocking of the filters and the level-ADC is based on a 38 kHz sampling frequency. A DC input signal is converted by a bitstream sigma-delta ADC followed by a decimation filter. The input signal has to be obtained from a radio part. The tuner must deliver the level information of either AM or FM to pin LEVEL. The input signal for level must be in the range 0 to 3.3 V (VVDACP - VVDACN). The 9-bit level-ADC converts this input voltage in steps with a resolution better than at least 14 mV over the 3.3 V range.
The tolerance on the gain is less than 2%. The MSB is always logic 0 to represent a positive level. Input level span can be increased by an external resistor tap. The high input impedance of the level-ADC makes this possible. The decimation filter reduces in the event of an 38 kHz based clocking regime the bandwidth of the incoming signal to a frequency range of 0 to 29 kHz with a resulting fs = 76 kHz. The response curve is given in Fig.9. The level information is sub-sampled by the DSP1 to obtain a field strength and a multipath indication. These values are stored in the coefficient or data RAM. Via the I2C-bus they can be read and used in other microcontroller programs.
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10
MGT465
(dB) 0
-10
-20
-30
-40
-50
-60
0
10
20
30
40
50
60
70
f (kHz)
80
Fig.9 Frequency response level-ADC and decimal filter.
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
8.4 Signal path from FM_MPX input to IAC and stereo decoder
SAA7706H
The FM_MPX signal is after selection available at one of three ADCs (ADC1, 2 and 3). The multiplex FM signal is converted to the digital domain in ADC1, 2 and 3 through a bitstream ADC. Improved performance for FM stereo can be achieved by means of adapting the noise shaper curve of the ADC to a higher bandwidth. The first decimation takes place in two down-sample filters. These decimation filters are switched by means of the I2C-bus bit wide_narrow in the wide or narrow band position. In the event of FM reception it must be in the narrow position.
After selection of one of the ADCs, the FM_MPX path it is followed by the IAC and the FM stereo decoder. One of the two MPX filter outputs contains the multiplex signal with a frequency range of 0 to 60 kHz. The overall low-pass frequency response of the decimation filters is shown in Fig.10.
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0
MGT466
(dB) -20 -40 -60 -80 -100 -120 -140 0 100 200 300 400 500
f (kHz)
Fig.10 Overall frequency response of ADC1, ADC2 and decimation filters.
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
The outputs of the stereo decoder to the DSP1, which are all running on a sample frequency of 38 kHz are: * Pilot presence indication: pilot-I. This 1-bit signal is LOW for a pilot frequency deviation <4 kHz and HIGH for a pilot frequency deviation >4 kHz and locked on a pilot tone. * `Left' and `right' FM reception stereo signal: this is the 18-bit output of the stereo decoder after the matrix decoding. * Noise level (see also Section 8.4.1): which is retrieved from the high-pass output of the MPX filter. The noise level is detected and filtered in the DSP1 and is used to optimize the FM weak signal processing.
SAA7706H
Normally the FM_MPX input and the FM_RDS input have the same source. If the FM input contains a stereo radio channel, the pilot information is switched to the Digitally Controlled Sampling (DCS) clock generation and the DCS clock is locked to the 256 x 38 kHz of the pilot. In this case this locked frequency is also used for the RDS path ensuring the best possible performance. Except from the above mentioned theoretical response also the non-flat frequency response of the ADC has to be compensated in the DSP1 program.
MGT467
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0
(dB) -20
-40
-60
-80
-100 0 10 20 30 40 50 60 f (kHz) 70
Fig.11 Transfer of MPX signal at the output of the stereo decoder.
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
8.4.1 NOISE LEVEL
SAA7706H
The high-pass 1 (HP1 or narrow band noise level filter) output of the second MPX decimation filter in a band from 60 kHz to 120 kHz is detected with an envelope detector and decimated to a frequency of 38 kHz. The response time of the detector is 100 s. Another option is the high-pass 2 (HP2 or wide band noise level filter). This output of the first MPX decimation filter is in a band from 60 to 240 kHz. It has the same properties and is also decimated to the same 38 kHz. Which of the signals is used (HP1 or HP2) is determined by the I2C-bus bit sel_nsdec.
The resulting noise information is rectified and has a word length of 10 bits. This means that the lowest and/or the highest possible level is not used. The noise level can be detected and filtered in the DSP1-core and be used to optimize the FM weak signal processing. The transfer curves of both filters before decimation are shown in Fig.12.
MGT468
handbook, full pagewidth
(dB)
0
(1)
-20 -40 -60 -80 -100 -120 -140 0
(2)
50
100
150
200
250
f (kHz)
300
(1) Noise with wide band digital filter. (2) Noise with small band digital filter.
Fig.12 Frequency response of noise level before decimation.
8.4.2
MONO OR STEREO SWITCHING
8.4.3
THE AUTOMATIC LOCK SYSTEM
The DCS block uses a sample rate converter to derive from the XTAL clock, via a PLL, a 512 multiple of 19 kHz (9.728 MHz). In the event of mono reception the DCS circuit generates a preset frequency of n x 19 kHz 2 Hz. In the event of stereo reception the frequency is exactly n x 19 kHz (DCS locked to N x pilot tone). The detection of the pilot and the stereo indication is done in the DSP program. 2001 Mar 05 20
The VCO of the DCS block will be at 19 kHz 2 Hz exact based in the event of no-pilot FM_MPX reception or in the event of only RDS reception. In the event of stereo reception the phase error is zero for a pilot tone with a frequency of exactly 19 kHz.
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
8.5 DCS clock
SAA7706H
In radio mode the stereo decoder, the ADC3 and RDS demodulator, the ADC1 or ADC2 and the level decimation filters have to run synchronously to the 19 kHz pilot. Therefore a clock signal with a controlled frequency of a multiple of 19 kHz (9.728 MHz = 512 x 19 kHz) is needed. In the SAA7706H the patented method of non-equidistant digitally controlled sampling DCS clock has been implemented. By a special dividing mechanism a frequency of 9.728 MHz from the PLL2 clock frequency of >40 MHz is generated. The dividing can be changed by means of I2C-bus bits to cope with the different input frequencies of the DCS block. The DCS system is controlled by up or down information from the stereo decoder. In the event of mono transmissions or 44.1 kHz ADC1 or ADC2 usage the DCS clock is still controlled by the stereo decoder loop. The output keeps the DCS free running on a multiple frequency of 19 kHz 2 Hz if the correct clock setting is applied. In tape/cd of either 38 or 44.1 kHz and AM mode the DCS clock always has to be put in preset mode with a bit in the I2C-bus memory map definitions. 8.6 8.6.1 The Interference Absorption Circuit (IAC) GENERAL DESCRIPTION
The characteristics of both IAC detectors can be adapted to the properties of different FM front-ends by means of the predefined coefficients in the IAC control registers. The values can be changed via the I2C-bus. Both IAC detectors can be switched on or off independently of each other. Both IAC detectors can mute the MPX signal independently of each other. A third IAC function is the dynamic IAC circuit. This block is intended to switch off the IAC completely the moment the MPX signal has a too high frequency deviation which in the event of small IF filters can result in AM modulation. This AM modulation could be interpreted by the IAC circuitry as interference caused by the car's engine. 8.7 The Filter Stream DAC (FSDAC)
The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales proportionally with the power supply voltage. 8.7.1 INTERPOLATION FILTER
The IAC detects and suppresses ignition interference. This hardware IAC is a modified, digitized and extended version of the analog circuit which is in use for many years already. The IAC consists of an MPX mute function switched by mute pulses from ignition interference pulse detectors. The input signal of a second IAC detection circuit is the FM level signal (the output of the level-ADC). This detector performs optimally in lower antenna voltage circumstances. It is therefore complementary to the first detector. The input signal of a first IAC detection circuit is the output signal of one of the down-sample paths coming from ADC1 or ADC2. This interference detector analyses the high-frequency contents of the MPX signal. The discrimination between interference pulses and other signals is performed by a special Philips patented fuzzy logic such as algorithm and is based on probability calculations. This detector performs optimally in higher antenna voltage circumstances. On detection of ignition interference, this logic will send appropriate pulses to the MPX mute switch.
The digital filter interpolates from 1 to 64fs by means of a cascade of a recursive filter and an FIR filter. Table 2 Digital interpolation filter characteristics ITEM Pass band ripple Stop band Dynamic range Gain 8.7.2 NOISE SHAPER CONDITIONS 0 - 0.45fs >0.55fs 0 - 0.45fs DC VALUE (dB) 0.03 -50 116.5 -3.5
The 5th-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter.
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
8.7.3 FUNCTION OF PIN POM
SAA7706H
With pin POM it is possible to switch off the reference current of the DAC. The capacitor on pin POM determines the time after which this current has a soft switch-on. So at power-on the current audio signal outputs are always muted. The loading of the external capacitor is done in two stages via two different current sources. The loading starts at a current level that is lower than the current loading after the voltage on pin POM has past a particular level. This results in an almost dB-linear behaviour. This must prevent `plop' effects during power on or off. 8.7.4 POWER-OFF PLOP SUPPRESSION
In order to obtain the lowest noise and to have the best ripple rejection, a filter capacitor has to be added between this pin and ground, preferably close to the analog pin VSSA2. 8.7.6 SUPPLY OF THE FILTER STREAM DAC
The entire analog circuitry of the DACs and the operational amplifiers are supplied by 2 supply pins: VDDA2 and VSSA2. VDDA2 must have sufficient decoupling to prevent total harmonic distortion degradation and to ensure a good power supply rejection ratio. The digital part of the DAC is fully supplied from the chip core supply. 8.8 Clock circuit and oscillator
To avoid plops in a power amplifier, the supply voltage of the analog part of the DAC and the rest of the chip can be fed from a separate power supply of 3.3 V. A capacitor connected to this power supply enables to provide power to the analog part at the moment the digital voltage is switching off fast. In this event the output voltage will decrease gradually allowing the power amplifier some extra time to switch off without audible plops. 8.7.5 PIN VREFDA FOR INTERNAL REFERENCE
With two internal resistors half the supply voltage VDDA2 is obtained and used as an internal reference. This reference voltage is used as DC voltage for the output operational amplifiers and as reference for the DAC.
The chip has an on-chip crystal clock oscillator. The block diagram of this Pierce oscillator is shown in Fig.13. The active element needed to compensate for the loss resistance of the crystal is the block Gm. This block is placed between the external pins OSC_IN and OSC_OUT. The gain of the oscillator is internally controlled by the AGC block. A sine wave with a peak-to-peak voltage close to the oscillator power supply voltage is generated. The AGC block prevents clipping of the sine wave and therefore the higher harmonics are as low as possible. At the same time the voltage of the sine wave is as high as possible which reduces the jitter going from sine wave to the clock signal.
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0.5VDD(OSC) AGC Gm clock to circuit Rbias
on-chip
63 OSC_IN 64 OSC_OUT 65 VDD(OSC) 62 VSS(OSC)
off-chip
C1 C2
MGT469
Fig.13 Block diagram oscillator circuit.
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
0.5VDD(OSC) AGC Gm clock to circuit Rbias
on-chip
63 OSC_IN 64 OSC_OUT 65 VDD(OSC) 62 VSS(OSC)
off-chip
C3 C1 C2
MGT470
slave input 3.3 V(p-p)
Fig.14 Block diagram of the oscillator in slave mode.
8.8.1
SUPPLY OF THE CRYSTAL OSCILLATOR
The power supply connections of the oscillator are separated from the other supply lines. This is done to minimize the feedback from the ground bounce of the chip to the oscillator circuit. Pin VSS(OSC) is used as ground supply and pin VDD(OSC) as positive supply. A series resistor plus capacitance is required for proper operating on pin VDD(OSC), see Figs 25 and 26. See also important remark in Section 8.10. 8.9 The phase-locked loop circuit to generate the DSPs and other clocks
* Although a multiple of the frequency of the used crystal of 11.2896 MHz falls within the FM reception band, this will not disturb the reception because the relatively low frequency crystal is driven in a controlled way and the sine wave of the crystal has in the FM reception band only very minor harmonics. 8.10 Supply of the digital part (VDDD3V1 to VDDD3V4)
The supply voltage on pins VDDD3V1 to VDDD3V4 must be for at least 10 ms earlier active than the supply voltage applied to pin VDD(OSC). 8.11 CL_GEN, audio clock recovery block
There are several reasons why a PLL circuit is used to generate the clock for the DSPs: * The PLL makes it possible to switch in the rare cases that tuning on a multiple of the DSP clock frequency occurs to a slightly higher frequency for the clock of the DSP. In this way an undisturbed reception with respect to the DSP clock frequency is possible. * Crystals for the crystal oscillator in the range of twice the required DSP clock frequency, so approximately 100 MHz, are always third overtone crystals and must also be manufactured on customer demand. This makes these crystals expensive. The PLL1 enables the use of a crystal running in the fundamental mode and also a general available crystal can be chosen. For this circuit a 256 x 44.1 kHz = 11.2896 MHz crystal is chosen. This type of crystal is widely used. 2001 Mar 05 23
When an external I2S-bus or SPDIF source is connected, the FSDAC circuitry needs an 256fs related clock. This clock is recovered from either the incoming WS of the digital serial input or the WS derived from the SPDIF1/SPDIF2 input. There is also a possibility to provide the chip with an external clock, in that case it must be a 256fs clock with a fixed phase relation to the source.
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
8.12 8.12.1 External control pins DSP1 8.13
SAA7706H
I2C-bus control (pins SCL and SDA)
For external control two input pins have been implemented. The status of these pins can be changed by applying a logic level. The status is saved in the DSP1 status register. The function of each pin depends on the DSP1 program. To control external devices two output pins are implemented. The status of these pins is controlled by the DSP program. Function of these `control pins' can be found in a separate manual and is rom_code dependent. 8.12.2 DSP2
General information about the I2C-bus can be found in "The I2C-bus and how to use it". This document can be ordered using the code 9398 393 40011. For the external control of the SAA7706H device a fast I2C-bus is implemented. This is a 400 kHz bus which is downward-compatible with the standard 100 kHz bus. There are two different types of control instructions: * Instructions to control the DSP program, programming the coefficient RAM and reading the values of parameters (level, multipath etc.) * Instructions controlling the data flow; such as source selection, IAC control and clock speed. The detailed description of the I2C-bus and the description of the different bits in the memory map is given in Chapter 9.
For external control four configurable I/O pins have been implemented. Via the I2C-bus these four pins can be independently configured as input or output. The status of these pins can be changed by applying a logic level (input mode). The status is saved in the DSP2 status register. The function of each pin depends on the I2C-bus setting and DSP2 program. Function of these `control pins' can be found in a separate manual and is rom_code dependent.
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
8.14 8.14.1 Digital serial inputs/outputs and SPDIF inputs GENERAL DESCRIPTION DIGITAL SERIAL AUDIO
INPUTS/OUTPUTS
SAA7706H
This chip does not handle the user data bits, channel status bits and validity bits of the SPDIF stream, but only the audio is given at its outputs. Some rom_codes do take care of the pre-emphasis bit of the SPDIF stream. The bits in the audio space are always decoded regardless of any status bits e.g. `copy protected', `professional mode' or `data mode'. The DAC is not muted in the event of a non-linear PCM audio, however the bit is observable via the I2C-bus. A few other channel status bits are available. There are 5 control signals available from the SPDIF input stage. These are connected to flags of DSP2. For more details see separate manual. These 5 control signals are: * Signals to indicate the sample frequency of the SPDIF signal: 44.1 and 48 kHz (32 kHz is not supported) * A lock signal indicating if the SPDIF input is in lock * The pre-emphasis bit of the SPDIF audio stream * The pcm_audio/non-pcm_audio bit indicating if an audio or data stream is detected. The FSDAC output will not be muted in the event of a non-audio PCM stream. This status bit can be read via the I2C-bus, the microcontroller can decide to mute the DAC (via pin POM). The design fulfils the digital audio interface specification "IEC 60958-1 Ed2, part 1, general part IEC 60958-3 Ed2, part 3, consumer applications". It should be noted that: * The SPDIF input may only be used in the `consumer mode' specified in the digital audio interface specification * Only one of the two SPDIF sources can be used (selected) at the same time * The FSDAC will not (automatically) be muted in the event of a non-audio stream * Two digital sources can not be used at the same time * Supported sample frequencies are 44.1 and 48 kHz.
For communication with external digital sources a digital serial bus is implemented. It is a serial 3-line bus, having one line for data, one line for clock and one line for the word select. For external digital sources the SAA7706H acts as a slave, so the external source is master and supplies the clock. The digital serial input is capable of handling multiple input formats. The input is capable of handling Philips I2S-bus and LSB-justified formats of 16, 18, 20 and 24 bits word sizes. The sampling frequency can be either 44.1 or 48 kHz. See Fig.15 for the general waveform formats of all possible formats. The number of bit clock (BCK) pulses may vary in the application. When the applied word length is smaller than 24 bits (internal resolution of DSP2), the LSB bits will get internally a zero value; when the applied word length exceeds 24 bits then the LSBs are skipped. It should be noted that: * Two digital sources can not be used at the same time * Maximum number of bit clocks per word select (WS) is limited to 64 * The word select (WS) must have a duty cycle of 50%. 8.14.2 GENERAL DESCRIPTION SPDIF INPUTS (SPDIF1 AND SPDIF2)
For communication with external digital sources also an SPDIF input can be used. The two SPDIF input pins can be connected via an analog multiplexer to the SPDIF receiver. It is a receiver without an analog PLL that samples the incoming SPDIF with a high frequency. In this way the data is recovered synchronously on the applied system clock. From the SPDIF signal a three wire serial bus (e.g. I2S-bus) is made, consisting of a word select, data and bit clock line. The sample frequency fs depends solely on the SPDIF signal input accuracy and both 44.1 and 48 kHz are supported.
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DATA MSB B2 B3 B4 B17 LSB LSB-JUSTIFIED FORMAT 18 BITS MSB B2 B3 B4 B17 LSB WS LEFT 20 BCK 19 18 17 16 15 2 1 RIGHT 20 19 18 17 16 15 2 1 DATA MSB B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS MSB B2 B3 B4 B5 B6 B19 LSB WS 24 BCK 23 22 21 LEFT 20 19 18 17 16 15 2 1 24 23 22 21 RIGHT 20 19 18 17 16 15 2 1 DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB LSB-JUSTIFIED FORMAT 24 BITS MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB
MGR751
8.14.3
Philips Semiconductors
handbook, full pagewidth
Car radio Digital Signal Processor (DSP)
DIGITAL DATA STREAM FORMATS
WS 1 BCK 2 3
LEFT >=8 1 2 3
RIGHT
>=8
DATA
MSB
B2
MSB
B2
MSB
INPUT FORMAT I2S-BUS
WS
LEFT 16 15 2 1
RIGHT 16 15 2 1
BCK
DATA
MSB
B2
B15 LSB LSB-JUSTIFIED FORMAT 16 BITS
MSB
B2
B15 LSB
WS
LEFT 18 17 16 15 2 1
RIGHT 18 17 16 15 2 1
BCK
Product specification
SAA7706H
Fig.15 All serial data input/output formats.
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
8.15 RDS demodulator (pins RDS_CLOCK and RDS_DATA) 8.15.1 CLOCK AND DATA RECOVERY
SAA7706H
The RDS demodulator recovers the additional inaudible RDS information which is transmitted by FM radio broadcasting. The (buffered) data is provided as output for further processing by a suitable decoder. The operational functions of the decoder are in accordance with the EBU specification "EN 50067". The RDS demodulator has three different functions: * Clock and data recovery from the MPX signal * Buffering of 16 bits, if selected * Interfacing with the microcontroller.
The RDS-chain has a separate input. This enables RDS updates during tape play and also the use of a second receiver for monitoring the RDS information of signals from an other transmitter (double tuner concept). It can as such be done without interruption of the audio program. The MPX signal from the main tuner of the car radio can be connected to this RDS input via the built-in source selector. The input selection is controlled by an I2C-bus bit. The RDS chain contains a sigma-delta ADC (ADC3), followed by two decimation filters. The first filter passes the multiplex band including the signals around 57 kHz and reduces the sigma-delta noise. The second filter reduces the RDS bandwidth around 57 kHz. The overall filter curve is shown in Fig.16 and a more detailed curve of the RDS 57 kHz band in Fig.17.
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MGT471
(dB) -20
-40
-60
-80
-100 0 19 38 57 76 95 114 133 f (kHz) 152
Fig.16 Overall frequency response curve decimation filters.
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
10
MGT472
(dB) 0 -10 -20 -30 -40 -50 -60 -70 50 52 54 56 58 60 62 f (kHz) 64
Fig.17 Detailed frequency response curve RDS channel.
The quadrature mixer converts the RDS band to the frequency spectrum around 0 Hz and contains the appropriate Q/I signal filters. The final decoder with CORDIC recovers the clock and data signals. These signals are output on pins RDS_CLOCK and RDS_DATA. In the event of FM-stereo reception the clock of the total chip is locked to the stereo pilot (19 kHz multiple). In the event of FM-mono the DCS loop keeps the DCS clock around the same 19 kHz multiple. In all other cases like AM reception or tape, the DCS circuit has to be set in a preset position by means of an I2C-bus bit. Under these conditions the RDS system is always clocked by the DCS clock in a 38 kHz (4 x 9.5 kHz) based sequence.
8.15.2
TIMING OF CLOCK AND DATA SIGNALS
The timing of the clock and data output is derived from the incoming data signal. Under stable conditions the data will remain valid for 400 s after the clock transition. The timing of the data change is 100 s before a positive clock change. This timing is suited for positive as well as negative triggered interrupts on a microcontroller. The RDS timing is shown in Fig.18. During poor reception it is possible that faults in phase occur, then the duty cycle of the clock and data signals will vary from minimum 0.5 times to a maximum of 1.5 times the standard clock periods. Normally, faults in phase do not occur on a cyclic basis.
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
RDS_DATA
RDS_CLOCK
tsu
Tcy
tHC
tLC
th
MGU270
Fig.18 RDS timing in the direct output mode.
8.15.3
BUFFERING OF RDS DATA
The repetition of the RDS data is around the 1187 Hz. This results in an interrupt on the microcontroller for every 842 s. In a second mode, the RDS interface has a double 16-bit buffer. 8.15.4 BUFFER INTERFACE
The RDS interface buffers 16 data bits. Every time 16 bits are received, the data line is pulled down and the buffer is overwritten. The microcontroller has to monitor the data line in at most every 13.5 ms. This mode can be selected via an I2C-bus.
In Fig.19 the interface signals from the RDS decoder and the microcontroller in buffer mode are shown. When the buffer is filled with 16 bits the data line is pulled down. The data line will remain LOW until reading of the buffer is started by pulling down the clock line. The first bit is clocked out. After 16 clock pulses the reading of the buffer is ready and the data line is set HIGH until the buffer is filled again. The microcontroller stops communication by pulling the line HIGH. The data is written out just after the clock HIGH-to-LOW transition. The data is valid when the clock is HIGH. When a new 16-bit buffer is filled before the other buffer is read, that buffer will be overwritten and the old data is lost.
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
RDS_DATA
D0
D1
D2
D13
D14
D15
tLC RDS_CLOCK tw block ready tHC Tcy start reading data
MGU271
Fig.19 Interface signals RDS decoder and microcontroller (buffer mode).
8.16
DSP reset
Pin DSP_RESET is active LOW and requires an external pull-up resistor. Between this pin and the VSSD ground a capacitor should be connected to allow a proper switch-on of the supply voltage. The capacitor value is such that the chip is in reset as long as the power supply is not stabilized. A more or less fixed relationship between the DSP_RESET (pin) and the POM (pin) time constant is mandatory. The voltage on pin POM determines the current flowing in the DACs. At 0 V on pin POM the DAC currents are zero and so are the DAC output voltages. At the VDDA2 voltage the DAC currents are at their nominal (maximal) value. Long before the DAC outputs get to their nominal output voltages, the DSP must be in working mode to reset the output register: therefore the DSP time constant must be shorter than the POM time constant. For recommended capacitors see Figs 25 and 26. The reset has the following function: * All I2C-bus bits are set to their default value * The DSP status registers (DSP1 and DSP2) are reset
* The program counter of both DSPs are set to address 0000H * The two output flags of DSP1 (DSP1_OUT1 and DSP1_OUT2) are reset to logic 0. All the configurable flags of DSP2 are reset to logic 0, however the four flags available at the output of the chip are default configured as input flags (DSP2_INOUT1, DSP2_INOUT2, DSP2_INOUT3 and DSP2_INOUT4). When the level on pin DSP_RESET is at HIGH, the DSP program (DSP1 and DSP2) starts to run. 8.17 Test mode connections (pins TSCAN, RTCB and SHTCB)
Pins TSCAN, RTCB and SHTCB are used to put the chip in test mode and to test the internal connections. Each pin has an internal pull-down resistor to ground. In the application these pins can be left open or connected to ground.
2001 Mar 05
30
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
9 I2C-BUS FORMAT
SAA7706H
For more general information on the I2C-bus protocol, see the Philips I2C-bus specification. 9.1 Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. 9.2 Slave address (pin A0)
Then the master writes the high memory address and low memory address where the reading of the memory content of the SAA7706H must start. The SAA7706H acknowledges these addresses both. Then the master generates a repeated START (Sr) and again the SAA7706H address `0011100' but this time followed by a logic 1 (read) of the R/W bit. From this moment on the SAA7706H will send the memory content in groups of 2 (Y-memory DSP1) or 3 (X-memory DSP1, X/Y-memory DSP2 or registers) bytes to the I2C-bus each time acknowledged by the master. The master stops this cycle by generating a negative acknowledge, then the SAA7706H frees the I2C-bus and the master can generate a STOP condition. The data is transferred from the DSP register to the I2C-bus register at execution of the MPI instruction in the DSP2 program. Therefore at least once every DSP routine an MPI instruction should be added. The data length of 4 bytes is not used in the SAA7706H. 9.5 SAA7706H hardware registers
The SAA7706H acts as slave receiver or a slave transmitter. Therefore the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The SAA7706H slave address is shown in Table 3. Table 3 MSB 0 0 1 1 1 0 A0 Slave address LSB R/W
The sub-address bit A0 corresponds to the hardware address pin A0 which allows the device to have 2 different addresses. The A0 input is also used in test mode as a serial input of the test control block. 9.3 Write cycles
The I2C-bus configuration for a write cycle is shown in Fig.20. The write cycle is used to write the bytes to both DSP1 and DSP2 for manipulating the data and coefficients. Depending on which DSP is accessed the data protocol exists out of 2, 3 or 4 bytes. More details can be found in the I2C-bus memory map (see Table 5). The data length is 2, 3 or 4 bytes depending on the accessed memory. If the Y-memory of DSP1 is addressed the data length is 2 bytes, in the event of the X-memory of DSP1 or X/Y-memory of DSP2 the length is 3 bytes. The slave receiver detects the address and adjusts the number of bytes accordingly. The data length of 4 bytes is not used in the SAA7706H. 9.4 Read cycles I2C-bus
The write cycle can be used to write the bytes to the hardware registers to control the DCS block, the PLL for the DSP clock generation, the IAC settings, the AD volume control settings, the analog input selection, the format of the I2S-bus and some other settings. It is also possible to read these locations for chip status information. More detail can be found in the I2C-bus memory map, Tables 4 and 5. 9.5.1 SAA7706H DSPS REGISTERS
The hardware registers have two different address blocks. One block exists out of hardware register locations which control both DSPs and some major settings such as the PLL division. These locations have a maximum of 16 bits, which means 2 bytes need to be sent to or read from. For the SAA7706H one register is located at the DSPs and general control register (0FFFH). The second block has an address space of 16 addresses and are all X-memory mapped on DSP2. While this space is 24 bits wide 3 bytes should be sent to or read from. These addresses are DSP2 mapped which means an MPI instruction is needed for accessing those locations and there is no verifying mechanism if all addresses are really mapped to physical registers. Therefore, all those locations will be acknowledged even if the data is not valid. For the SAA7706H several registers are located in this section. A few registers are predefined for DSP2 purposes (see Table 5).
The configuration for a READ cycle is shown in Fig.21. The read cycle is used to read the data values from XRAM or YRAM of both DSPs. The master starts with a START condition S, the SAA7706H address `0011100' and a logic 0 (write) for the R/W bit. This is followed by an acknowledge of the SAA7706H.
2001 Mar 05
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A
Philips Semiconductors
Car radio Digital Signal Processor (DSP)
S00111000C
K
ADDR H
A C K
ADDR L
A C K
DATA H
A C K
DATA M
A C K
DATA L
A CP K
auto increment if repeated n-groups of 3 (2) bytes address R/W
MGD568
S = START condition P = STOP condition ACK = acknowledge from SAA7706H ADDR H and ADDR L = address DSP register DATA 1, DATA 2, DATA3 and DATA 4 = 2, 3 or 4 bytes data word.
Fig.20 Master transmitter writes to the SAA7706H registers. 32
A
S00111000C
K
ADDR H
A C K
ADDR L
A A CS00111001C K K
DATA H
A C K
DATA M
A C K
DATA L
A CP K
auto increment if repeated n-groups of 3 (2) bytes address R/W R/W
MGA808 - 1
S = START condition Sr = repeated START condition P = STOP condition ACK = acknowledge from SAA7706H (SDA LOW) R = repeat n-times the 2, 3 or 4 bytes data group NA = negative acknowledge master (SDA HIGH) ADDR H and ADDR L = address DSP register DATA 1, DATA 2, DATA 3 and DATA 4 = 2, 3 or 4 bytes data word.
Product specification
SAA7706H
Fig.21 Master transmitter reads from the SAA7706H registers.
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
9.6 I2C-bus memory map specification
SAA7706H
The I2C-bus memory map contains all defined I2C-bus bits. The map is split up in two different sections, the hardware memory registers and the RAM definitions. In Table 5 the preliminary memory map is depicted. The hardware registers are memory map on the XRAM of DSP2. Table 5 shows the detailed memory map of those locations. All locations are acknowledged by the SAA7706H even if the user tries to write to a reserved space. The data in these sections will be lost. Reading from this locations will result in undefined data words. Table 4 I2C-bus memory map ADDRESS 2000H to 21FFH 1FF0H to 1FFFH 1000H to 127FH 0FFFH 0800H to 097FH 0000H to 017FH Table 5 YRAM (DSP2) hardware registers XRAM (DSP2) DSP CONTROL YRAM (DSP1) XRAM (DSP1) FUNCTION 512 x 12 bits 16 x 24 bits 640 x 24 bits 1 x 16 bits 384 x 12 bits 384 x 18 bits SIZE
I2C-bus memory map overview of hardware registers DESCRIPTION REGISTER
Hardware registers Program counter register DSP2 Status register DSP2 I/O configuration register DSP2 Phone, navigation and audio register FM and RDS sensitivity register Clock coefficient register Clock settings register IAC settings register Selector register CL_GEN register 4 CL_GEN register 3 CL_GEN register 2 CL_GEN register 1 Evaluation register DSP control DSPs and general control register 0FFFH 1FFFH 1FFEH 1FFDH 1FFCH 1FFBH 1FFAH 1FF9H 1FF8H 1FF7H 1FF6H 1FF5H 1FF4H 1FF3H 1FF0H
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
10 LIMITING VALUES In accordance with the Absolute Maximum Ratings System (IEC 60134). SYMBOL VDD Vn IIK IOK IO(sink/source) IDD,ISS Tamb Tstg VESD PARAMETER supply voltage input voltage on any pin DC input clamping diode current DC output clamping diode current supply current per supply pin ambient operating temperature storage temperature range ESD voltage human body model machine model Ilu(prot) Ptot latch-up protection current total power dissipation 100 pF; 1500 200 pF; 0.5 H; 10 CIC spec/test method 2000 200 100 - VI < -0.5 V or VI > VDD + 0.5 V VO < -0.5 V or VO > VDD + 0.5 V CONDITIONS MIN. -0.5 -0.5 - - - - -40 -65
SAA7706H
MAX. +3.6 +5.5 10 20 20 50 +85 +125 - - - 890 V V
UNIT
mA mA mA mA C C V V mA mW
DC output source or sink current -0.5 V < VO < VDD + 0.5 V
11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS mounted on printed-circuit board VALUE 45 UNIT K/W
12 CHARACTERISTICS VDD = 3 to 3.6 V; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies; Tamb = -40 to +85 C VDD IDDD IDDD(core) IDDD(peri) IDDA IDDA(ADC) IDDA(DAC) IDDA(osc) operating supply voltage supply current of the digital part supply current of the digital core part supply current of the digital periphery part supply current of the analog part supply current of the ADCs supply current of the DACs supply current XTAL oscillator all VDD pins with respect to VSS DSP1 at 50 MHz; DSP2 at 62.9 MHz DSP1 at 50 MHz; DSP2 at 62.9 MHz without external load to ground zero input and output signal zero input and output signal zero input and output signal functional mode 3.0 - - - - - - - 3.3 110 105 5 40 15 19 2 3.6 150 140 10 60 26 30 4 V mA mA mA mA mA mA mA
2001 Mar 05
34
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
SYMBOL Ptot
PARAMETER total power dissipation
CONDITIONS DSP1 at 50 MHz, DSP2 at 62.9 MHz -
MIN.
TYP. 540
MAX. 750
UNIT mW
Digital I/O; Tamb = -40 to +85 C; VDD = 3 to 3.6 V VIH HIGH-level input voltage for all digital inputs and I/Os LOW-level input voltage for all digital inputs and I/Os Schmitt trigger hysteresis voltage HIGH-level output voltage standard output; IO = -4 mA 5 ns slew rate output; IO = -4 mA 10 ns slew rate output; IO = -2 mA 20 ns slew rate output; IO = -1 mA VOL LOW-level output voltage standard output; IO = 4 mA 5 ns slew rate output; IO = 4mA 10 ns slew rate output; IO = 2 mA 20 ns slew rate output; IO = 1 mA I2C-bus output; IO = 4 mA ILO Rpd Rpu Ci ti(r),ti(f) to(t) output leakage current 3-state outputs internal pull-down resistor to VSS internal pull-up resistor to VDD input capacitance input rise and fall times output transition time VDD = 3.6 V standard output; CL = 30 pF 5 ns slew rate output; CL = 30 pF 10 ns slew rate output; CL = 30 pF 20 ns slew rate output; CL = 30 pF I2C-bus output; Cb = 400 pF VO = 0 V or VDD 2.0 - - V
VIL
-
-
0.8
V
Vhys VOH
0.4 VDD - 0.4 VDD - 0.4 VDD - 0.4 VDD - 0.4 - - - - - - 24 30 - - - - - - 60
- - - - - - - - - - - 50 50 - 6 3.5 5 10 20 -
- - - - - 0.4 0.4 0.4 0.4 0.4 5 140 100 3.5 200 - - - - 300
V V V V V V V V V V A k k pF ns ns ns ns ns ns
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog inputs; Tamb = 25 C; VDDA1 = 3.3 V DC CHARACTERISTICS V VREFAD --------------------V VDDA1 Zo(VREFAD) VVDACP IVDACP VVDACN1, VVDACN2 IVDACN1, IVDACN2 VIO(ADC) common mode reference voltage ADC1, ADC2 and level-ADC output impedance at pin VREFAD positive reference voltage ADC1, 2, 3 and level-ADC positive reference current ADC1, 2, 3 and level-ADC negative reference voltage ADC1, 2, 3 and level-ADC negative reference current ADC1, 2 and 3 input offset voltage ADC1, 2 and 3 with reference to VSSA1 0.47 0.50 0.53
- 3 - -0.3
10 3.3 -200 0
- 3.6 - +0.3
V A V
- -
200 140
- -
A mV
AC CHARACTERISTICS Vi(con)(max)(rms) maximum conversion input level (RMS value) CD, TAPE, AM and AUX input signals FM_MPX input signal Ri input impedance CD, TAPE, AM and AUX input signals FM_MPX input signal THD total harmonic distortion CD, TAPE, AM and AUX input signals FM_MPX input signal input signal 0.55 V (RMS) at 1 kHz; bandwidth = 20 kHz; fs = 44.1 kHz - -85 -75 dB 1 48 - 60 - 72 M k THD <1% THD <1%; VOLFM = 00H 0.6 0.33 0.66 0.368 - - V V
input signal 368 mV (RMS) at - 1 kHz; bandwidth = 19 kHz; - VOLFM = 00H
-70 0.03
-65 0.056
dB %
2001 Mar 05
36
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
SYMBOL S/N
PARAMETER signal-to-noise ratio CD, TAPE, AM and AUX input signals
CONDITIONS input signal at 1 kHz; bandwidth = 20 kHz; 0 dB reference = 0.55 V (RMS); fs = 44.1 kHz input signal at 1 kHz; bandwidth = 19 kHz; 0 dB reference = 0.368 V (RMS); VOLFM = 00H input signal at 1 kHz; bandwidth = 40 kHz; 0 dB reference = 0.368 V (RMS); VOLFM = 00H pilot signal frequency = 19 kHz unmodulated subcarrier frequency = 38 kHz unmodulated subcarrier frequency = 57 kHz unmodulated subcarrier frequency = 76 kHz unmodulated fmod = 10 kHz; fspur = 1 kHz fmod = 13 kHz; fspur = 1 kHz f = 57 kHz f = 67 kHz 85
MIN.
TYP. 90 -
MAX.
UNIT dB
FM_MPX input signal mono
80
83
-
dB
FM_MPX input signal stereo
75
81
-
dB
19
carrier and harmonic suppression at the output carrier and harmonic suppression at the output carrier and harmonic suppression for 19 kHz, including notch carrier and harmonic suppression for 19 kHz, including notch intermodulation intermodulation traffic radio suppression Subsidiary Communication Authority (SCA) suppression adjacent channel suppression adjacent channel suppression pilot threshold voltage (RMS value) at pin DSP1_OUT1 hysteresis of Vth(pilot)(rms) channel separation FM-stereo input channel separation CD, TAPE, AM and AUX input signals
- - - - - - - - 77 76 - -
81 98 83 91 83 96 84 94 - - 110 110
- - - - - - - - - - - -
dB dB dB dB dB dB dB dB dB dB dB dB
38
57
76
IM10 IM13 57(VF) 67(SCA)
114 190 Vth(pilot)(rms)
f = 114 kHz f = 190 kHz stereo on; VOLFM = 07H stereo off; VOLFM = 07H
- - - - -
110 110 35.5 35.4 0 45 30 70
- - - - - - - -
dB dB mV mV dB dB dB dB
hys cs1 cs2
fi = 1 kHz fi = 10 kHz
40 25 60
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
SYMBOL fres
PARAMETER audio frequency response CD, TAPE, AM and AUX input signals FM_MPX input signal
CONDITIONS fs = 44.1 kHz; at -3 dB at -3 dB via DSP at DAC output 20 17 -
MIN. - - -
TYP. - -
MAX.
UNIT kHz kHz dB
GL-R
overall left/right gain unbalance (TAPE, CD, AUX and AM input signals) crosstalk between inputs power supply ripple rejection MPX and RDS ADCs fi = 1 kHz fi = 15 kHz I2S-bus;
0.5
ct PSRRMPX/RDS
65 50
- - 45
- - -
dB dB dB
output via ADC input 35 short-circuited; fripple = 1 kHz; Vripple = 100 mV (peak); CVREFAD = 22 F; CVDACP = 10 F output via DAC; ADC input 29 short-circuited; fripple = 1 kHz; Vripple = 100 mV (peak); CVREFAD = 22 F RCD_(L)_GND = 1 M; resistance of CD player ground cable < 1 k; fi = 1 kHz 60
PSRRLAD
power supply ripple rejection level-ADC
39
-
dB
CMRRCD
common-mode rejection ratio for CD input mode
-
-
dB
AC characteristics PHONE and NAV inputs; Tamb = 25 C; VDDA1 = 3.3 V THD total harmonic distortion of PHONE and NAV input signals at maximum input voltage common mode rejection ratio of PHONE and NAV input signals input impedance of PHONE, NAV/AM_L and AM_R input signals maximum input level of PHONE and NAV input signals (RMS value) fi = 1 kHz; VOLMIX = 30H Vi = 0.75 V (RMS); fi = 1 kHz; 40 VOLMIX = 30H; measured at FLV and FRV outputs Vi = 0.75 V(RMS); fi = 1 kHz; 25 VOLMIX = 30H 90 - - dB
CMRR
50
-
dB
Ri
120
150
k
Vi(max)(rms)
0.75
1
-
V
AC characteristics FM_RDS input; Tamb = 25 C; VDDA1 = 3.3 V Vi(con)(max)(rms) maximum conversion level THD < 1%; VOLRDS = 00H of FM_RDS input (RMS value) input resistance FM_RDS input total harmonic distortion RDS ADC fc = 57 kHz 0.33 0.368 - V
Ri(FM_RDS) THDFM_RDS
40 -60
60 -67
72 -
k dB
2001 Mar 05
38
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
SYMBOL S/NFMRDS
PARAMETER signal-to-noise ratio RDS ADC pilot attenuation RDS nearby selectivity RDS RDS ADC noise attenuation ripple voltage RDS pass band
CONDITIONS 6 kHz bandwidth; fc = 57 kHz; 54 0 dB reference = 0.55 V (RMS); VOLRDS = 00H 50 neighbouring channel at 200 kHz distance 61 70 2.4 kHz bandwidth - 70 40 -
MIN. -
TYP. -
MAX.
UNIT dB
pilot n(ADC) Vripple(RDS) mux(RDS) fosc
- - - - - - -
- - - 0.5 - - 6
dB dB dB dB dB dB Hz
multiplex attenuation RDS mono stereo allowable frequency deviation of the 57 kHz RDS maximum crystal resonance frequency deviation of 100 ppm
AC characteristics SPDIF1 and SPDIF2 inputs; Tamb = 25 C; VDDA2 = 3.3 V Vi(p-p) Ri Vhys AC input level (peak-to-peak level) input impedance hysteresis of input voltage at 1 kHz 0.2 - - 0.5 6 40 3.3 - - - V k mV
AC characteristics analog LEVEL input; Tamb = 25 C; VDDA1 = 3.3 V S/NLAD signal-to-noise ratio of level-ADC input resistance full-scale level-ADC input voltage DC offset voltage decimation filter attenuation pass band cut-off frequency sample rate frequency after decimation at -3 dB and DCS clock = 9.728 MHz DCS clock = 9.728 MHz 0 to 29 kHz bandwidth; maximum input level; unweighted 48 54 dB
Ri Vi(fs)(LAD) VIO fco(PB) fsr
1.0 0 - 20 - -
- - - - 29 38
2.2 VDDA1 120 - - -
M V mV dB -----------------decade kHz kHz
Analog DAC outputs on pins FLV, FRV, RLV and RRV; Tamb = 25 C; VDDA2 = 3.3 V; fs = 44.1 kHz; RL = 5 k; fi = 1 kHz DC CHARACTERISTICS Ro(ref) Ro Io(max) RL 2001 Mar 05 reference output resistance DAC output resistance maximum output current load resistance 39 pin VREFDA pins FLV, FRV, RLV and RRV (THD + N)/S < 0.1%; RL = 5 k - - - 3 14 0.13 0.22 - - 3.0 - - k mA k
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
SYMBOL CL Vo(RMS) Vo (THD + N)/S
PARAMETER load capacitance
CONDITIONS - - - at 0 dB at -60 dB; A-weighted - - -
MIN. -
TYP.
MAX. 200 - - -85 - -
UNIT pF
AC CHARACTERISTICS output voltage (RMS value) unbalance between channels total harmonic distortion-plus-noise to signal ratio (measured with system one) signal-to-noise ratio (measured with system one) channel separation power supply rejection ratio 1000 0.1 -90 -37 mV dB dB dB
S/N
code = 0; A-weighted
105
dB
cs PSRR
- fripple = 1 kHz; Vripple(p-p) = 1% -
80 50
- -
dB dB
Oscillator; Tamb = 25 C; VDD(OSC) = 3.3 V fxtal Vxtal crystal frequency voltage across the crystal crystal series resistance Rs < 100 ; crystal shunt capacitance Cp < 7 pF; crystal load capacitance CL = 12 pF; C1 = C2 = 22 pF (see Fig.13) at start-up at oscillation - 1.6 11.2896 - 2.6 3.6 MHz V
IDD(OSC)
supply current crystal oscillator
1.7 -
3.4 0.32
6.4 -
mA mA
13 RDS AND I2S-BUS TIMING Tamb = 25 C; VDDD = 3.3 V; unless otherwise specified. SYMBOL PARAMETER CONDITIONS - direct output mode direct output mode buffer mode tHC tLC th tw clock HIGH time clock LOW time data hold time wait time buffer mode direct output mode buffer mode direct output mode buffer mode 100 - 2 220 1 220 1 100 1 MIN. TYP. - - - - 640 - 640 - - - MAX. UNIT
RDS timing (see Figs 18 and 19) fRDSCLK tsu Tcy nominal RDS clock frequency clock set-up time cycle time 1187.5 - 842 - - - - - - - Hz s s s s s s s s s
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2S-bus timing (see Fig.23) tr tf Tcy tBCK(H) tBCK(L) tsu(D) th(D) td(D) tsu(WS) th(WS) rise time fall time bit clock cycle time bit clock time HIGH bit clock time LOW data set-up time data hold time data delay time word select set-up time word select hold time Tcy = 325 ns Tcy = 325 ns Tcy = 325 ns Tcy = 325 ns Tcy = 325 ns Tcy = 325 ns Tcy = 325 ns Tcy = 325 ns Tcy = 325 ns - - 325 0.35Tcy 0.35Tcy 0.2Tcy 0.2Tcy - 0.2Tcy 0.2Tcy - - - - - - - - - - 0.15Tcy 0.15Tcy - - - - - 0.15Tcy - - ns ns ns ns ns ns ns ns ns ns
handbook, full pagewidth
LEFT
WS RIGHT tBCK(H) tr tf th(WS) td(D) tsu(WS)
BCK tBCK(L) Tcy LSB MSB tsu(D) th(D)
DATA IN
DATA OUT
LSB
MSB
MGM129
Fig.23 Input timing digital audio data inputs.
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
14 I2C-BUS TIMING Tamb = 25 C; VDDD = 3.3 V; unless otherwise specified. STANDARD MODE I2C-BUS MIN. fSCL tBUF SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition data hold time data set-up time rise time of both SDA and SCL signals Cb in pF 0 4.7 - MAX. 100 0 1.3
SAA7706H
FAST MODE I2C-BUS UNIT MIN. - MAX. 400 kHz s
SYMBOL
PARAMETER
CONDITIONS
tHD;STA
4.0
-
0.6
-
s
tLOW tHIGH tSU;STA
4.7 4.0 4.7
- - -
1.3 0.6 0.6
- - -
s s s
tHD;DAT tSU;DAT tr tf tSU;STO Cb tSP
0 250 - - 4.0 - -
- - 1000 300 - 400 -
0 100 20 + 0.1Cb 20 + 0.1Cb 0.6 - 0
0.9 - 300 300 - 400 50
s ns ns ns s pF ns
fall time of both SDA and Cb in pF SCL signals set-up time for STOP condition capacitive load for each bus line pulse width of spikes to be suppressed by input filter
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
SDA tf
tf
tLOW
tr
tSU;DAT
tHD;STA
tSP
tr
tBUF
SCL tHD;STA tSU;STA tSU;STO
S
tHD;DAT
tHIGH
Sr
P
S
MSC610
Fig.24 Definition of timing on the I2C-bus.
15 SOFTWARE DESCRIPTION The use and description of the software features of the SAA7706H will be described in the separate application manual. 16 APPLICATION DIAGRAM The application diagram shown in Figs 25 and 26 must be considered as one of the examples of a (limited) application of the chip e.g. in this case the I2S-bus inputs of the CD-input are not used. For the real application set-up the information of the application report is necessary.
2001 Mar 05
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Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
VDDA
VDDD R35 10
L2 R34
C45 22 nF
VDDD3V5
VDDD3V6
VDDD3V7
VSSD3V1
VSSD3V2
VSSD3V3
VSSD3V4
VSSD3V5
VSSD3V6
VDACP C43 100 F C1 PHONE R1 R3 100 k C3 220 pF 470 nF 15 k C2 R2 470 nF 15 k R4 LEVEL 27 k C6 CD-L 1 F R6 8.2 k R8 10 k R9 10 k C9 100 pF C10 100 pF C4 220 pF R5 100 k VDACN1
1 2
74
76 75
46 36 22
49 50 53 54 47 37 23
PHONE 71 MONO CMRR INPUTS
PHONE_GND C5
73
VSSD3V7
10 VDACN2 VDDA1 VSSA1
A
NAV_GND LEVEL
4 3 LEVEL ADC
220 nF
B
CD_L 72
CD-GND C8 CD-R
C7 47 F R7 8.2 k
CD_(L)_GND
77
CD_R CD_R_GND R10 1 M VREFAD
70 14
STEREO CMRR INPUTS
1 F
SAA7706H
78
C11 47 nF C13 AM-L/NAV 220 nF C15 AM-R/AM 220 nF C17 TAPE-L 220 nF C19 TAPE-R 220 nF AUX-L 220 nF AUX-R 220 nF FM 22 k C21 27 pF 82 k R19 C48 100 pF 82 k R39 C47 100 pF 56 k R37 C20 100 pF 56 k R17 C18 100 pF 100 k C16 R15 100 pF 100 k C14 R13 100 pF R11
C12 22 F AM_L/NAV 67 STEREO ADC1 AM_R/AM R16 100 k R18 100 k R38 100 k R39 100 k AUX_R FM_RDS C22 1 F FM_MPX SEL_FR 8 79 80 61 RDS DEMODULATOR XTAL OSCILLATOR AUX_L 7 TAPE_R 68 ANALOG SOURCE SELECTOR MONO ADC3 TAPE_L 69 66 STEREO ADC2
C
D
E
43 44 45 RTCB SHTCB TSCAN
21 TP1
60 RDS_DATA
59 62 65 RDS_CLOCK VDD(OSC) VSS(OSC)
63 OSC_IN
64 OSC_OUT X1 C25 18 pF
MGT473
C23 100 nF L1 C24 18 pF C48 47 F
RDS RDS DATA CLOCK R36 10
11.2896 MHz
VDDA
Fig.25 Application diagram (continued in Fig.26).
2001 Mar 05
44
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
VDDD DSP-FLAGS VDDD R37 4.7 k DSP2_INOUT3 DSP2_INOUT2 DSP2_INOUT1 +5 V
DSP2_INOUT4
DSP1_OUT2
DSP1_OUT1
DSP1_IN2
DSP1_IN1
VDDD3V1
VDDD3V2
VDDD3V3
VDDD3V4
R24 910 T1 R25 4.7 k 11 VDDA2 10 VSSA2 5 POM C33 22 F C31 22 F C32 100 nF microcontroller
48 51 52 55
41 40 39 38 19 18 15 17
A
PHONE VOLUME C34 10 F
B
SIGNAL LEVEL
+ +
DSP1 QUAD FSDAC
16 FLV
R27 R26 10 k 100 FRONT-LEFT C35 10 nF
SIGNAL QUALITY
13 FRV
C36 10 F R28 10 k
R29 100 FRONT-RIGHT C37 10 nF
SAA7706H
9 RLV
C38 10 F R30 10 k
R31 100 REAR-LEFT C39 10 nF
C
IAC
STEREO DECODER DIGITAL SOURCE SELECTOR 6 RRV C40 10 F
R33 R32 10 k 100 REAR-RIGHT C41 10 nF
D
E
12 VREFDA C42 4.7 F
A DIGITAL SOURCE B SELECTORS DSP2 DIGITAL I/O
34 IIS_OUT1 35 IIS_OUT2 30 IIS_CLK 33 IIS_WS 31 IIS_IN1 32 IIS_IN2
I2S-BUS
SPDIF
I2C-BUS 20 LOOPO
26 SYSFS
29 27 28 CD_DATA CD_WS CD_CLK
24 25 SPDIF2 SPDIF1
57 SCL
58 SDA
56 A0
42 DSP_RESET
C27 SPDIF2 C26 100 pF R20 100 nF 75 C29 SPDIF1 C28 100 pF R21 100 nF 75 SCL SDA R22 10 k +5 V R23 10 k +5 V
microcontroller C30 1 F
MGT474
Fig.26 Application diagram (continued from Fig.25).
2001 Mar 05
45
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
17 PACKAGE OUTLINE QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAA7706H
SOT318-2
c
y X
64 65
41 40 ZE
A
e E HE wM pin 1 index bp 25 1 wM D HD ZD B vM B 24 vMA Lp L detail X A A2 A1 (A 3)
80
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-2 REFERENCES IEC JEDEC MO-112 EIAJ EUROPEAN PROJECTION A max. 3.2 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.45 0.30 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.8 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 7 0o
o
ISSUE DATE 97-08-01 99-12-27
2001 Mar 05
46
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
18 SOLDERING 18.1 Introduction to soldering surface mount packages
SAA7706H
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 18.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 18.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2001 Mar 05
47
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
18.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SAA7706H
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2001 Mar 05
48
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
19 DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
SAA7706H
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 20 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22 PURCHASE OF PHILIPS I2C COMPONENTS 21 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2001 Mar 05
49
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
NOTES
SAA7706H
2001 Mar 05
50
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
NOTES
SAA7706H
2001 Mar 05
51
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2001
Internet: http://www.semiconductors.philips.com
SCA 71
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/25/01/pp52
Date of release: 2001
Mar 05
Document order number:
9397 750 07096

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